Sr. ASIC/FPGA Design Engineer (DSP)

Company: SpaceX
Location: Irvine
Posted on: October 14, 2020

Job Description:

Sr. ASIC/FPGA Design Engineer (DSP) at SpaceX Irvine, CA, United States SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC/FPGA DESIGN ENGINEER (DSP) Would you like to become part of a team developing silicon solutions for a cutting-edge low Earth orbit satellite communication system that delivers world-wide broadband connectivity to the people who either do not have access to the Internet or have spotty connectivity? Come join the Starlink silicon team working on ASIC and FPGA projects that drive more integration, lower power, mixed-signal architectures, and next generation technology to be deployed in space and ground infrastructures. In this job, you will focus on digital signal processing (DSP) and digital communication system blocks as part of complex ASIC and FPGA SoC products and will participate in numerous exciting and challenging activities as part of our fast-paced silicon design process. RESPONSIBILITIES: - Participate in all phases of ASIC/FPGA design flow - from concept to mass production - Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, create specification documents - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.) - Optimize your designs for area, speed, and power to meet system requirements; analyze architectural trade-offs - Develop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checking - Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers - Collaborate with verification engineers to develop UVM-based top-level tests for your blocks - Participate in SoC-level and FPGA top-level integration activities - Prototype designs on FPGA, focusing on closely emulating the final product functionality - Use scripting languages to achieve higher performance and improve productivity through automation - Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks - Run implementation tools, such as Synopsys Design Compiler, Xilinx Vivado, and others; perform timing closure for your designs - Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs - Bring-up and validate ASICs and FPGAs in the lab, utilize various lab equipment - Collaborate with software engineers in developing production software for your designs BASIC QUALIFICATIONS: - Master's degree or PhD in electrical engineering, computer engineering or other engineering discipline - 8+ years of experience in working with ASICs and FPGAs - 8+ years of experience in SystemVerilog, Verilog, or VHDL RTL design - 8+ years of experience in designing DSP and digital communication system datapath blocks (e.g. filters, transforms, PHY blocks, loops, FEC, etc.) - 8+ years of experience in scripting and programming languages (MATLAB, Python, C/C++, Perl, Tcl, Make, Bash - three or more from this list) PREFERRED SKILLS AND EXPERIENCE: - Strong theoretical knowledge of basic concepts in DSP and digital communication systems - Expert knowledge of SystemVerilog, Verilog, and/or VHDL - Strong experience in designing signal processing and digital communications circuits, experience in modem design - Equally strong knowledge in designing datapath and control RTL blocks - Strong programming and scripting skills in most of these languages: MATLAB, Python, C/C++, Perl, Tcl, Make, Bash - Strong knowledge of clock domain crossing (CDC) techniques - Strong expertise in Xilinx advanced FPGAs, eval boards, and strong knowledge of FPGA design flow - Expertise in different DSP architectures and tradeoffs (including transforms, filtering, sample rate conversion, etc.) - Good knowledge of different digital modulation techniques (e.g. PSK, QAM, OFDMA, etc.) - Good knowledge of or experience in wireless communications systems and standards (e.g. LTE, Wi-Fi, Bluetooth, etc.) - Good knowledge of or experience in designing high-speed forward error correction (FEC) blocks, such as LDPC, Turbo Codes, convolutional/Viterbi, and Reed-Solomon codecs - Good knowledge of or experience in industry standard interfaces, protocols, and architectures: PCIe, Ethernet, AMBA, and DDR - Expertise in developing automated, self-checking test benches - Experience in UVM verification framework - Good experience in EDA tools such as simulators (e.g. Questa), lint checkers (e.g. Spyglass), synthesis (e.g. Design Compiler), FPGA tools (e.g. Vivado) - Good experience in synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs, knowledge of STA tools (e.g. PrimeTime) - Experience in formal verification and logic equivalence checking, knowledge of LEC tools (e.g. Formality) - Knowledge of power optimization, power estimation, UPF-based power verification - Experience in ASIC/FPGA/SoC system-level/top-level integration - Experience in design for testability (DFT) and high reliability ASIC design and implementations - Experience in Git version control system - Experience in Atlassian collaboration and automation tools: JIRA, Confluence, Bitbucket, Bamboo, etc. - Strong interpersonal, written, and verbal communication skills; ability to work well in a diverse environment, good cross-functional communication skills - Team-player, can-do attitude, and ability to work well in a group environment, while still contributing on an individual basis - Strong problem solving skills with appropriate attention to detail - High level of self-motivation, enjoys being challenged and learning new skills - Ability to work in a dynamic, fast-paced environment with changing needs and requirements; ability to meet tough goals under high pressure and manage your time effectively ADDITIONAL REQUIREMENTS: - Willing to work extended hours and weekends as needed - Willing to travel when needed (typically

Keywords: SpaceX, Irvine , Sr. ASIC/FPGA Design Engineer (DSP), Engineering , Irvine, California