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UVM Verification Engineer

Company: ASICSOFT
Location: Irvine
Posted on: January 17, 2020

Job Description:

LOCATION: Irvine, CA -OR- Redmond, WA (onsite req'd) DURATION: Full-time, permanent TITLE: UVM Verification Engineer ROLE: Digital Verification (ASIC/FPGA) at the block and system level Write test plans, harnesses, and sequences using UVM and SystemVerilog Executing test plans, regression running, code and functional coverage closure Contribution to pre-si verification, bring-up, post-si validation Full verification of a complex digital design EXPERIENCE: Experience with UVM, OVM, or VMM Experience developing test plans, defining/implementing coverage models, and analyzing results Experience creating scalable verification environments Experience writing scripts (bash/csh, Python, Perl, TCL, etc.) for automation Experience with simulators (Questa, VCS, IES), code coverage tools, debug tools (Verdi, Visualizer), and bug tracking tools Strong object-oriented programming knowledge Experience with constrained random verification Experience with dynamic simulation and/or formal based verification methodologies Some experience with packet based protocols (PCIe, ethernet), or wireless protocols (LTE, Wi-Fi), or DSP algorithms is preferred Experience testing complex designs, code and functional coverage, and assertions - provided by Dice

Keywords: ASICSOFT, Irvine , UVM Verification Engineer, Engineering , Irvine, California

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