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Senior ASIC DV Engineer

Company: Broadcom Inc.
Location: Irvine
Posted on: January 16, 2020

Job Description:

JOB DESCRIPTION:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

Architect block and full-chip verification environments using HVLs and constrained random techniques (UVM) for SOCs with embedded CPUs and mixed signal interfaces.

Develop test plans and coverage metrics from specifications and write block and chip-level tests.

Debug RTL and Gate simulations and work with design engineers to verify fixes.

Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.

Replicate silicon bugs in simulation environment and validate fixes or SW workarounds.

Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.

Knowledge of C, Low Power Verification (UPF) and Mixed-signal simulations (AMS, Spice) etc.

Assist in the development of embedded FW.

MS / PhD is preferred. 12+ years experience.


IF YOU ARE LOCATED OUTSIDE USA, PLEASE BE SURE TO FILL OUT A HOME ADDRESS AS THIS WILL BE USED FOR FUTURE CORRESPONDENCE.

Broadcom Inc. is committed to creating a diverse work environment and is proud to be an equal opportunity employer.

Keywords: Broadcom Inc., Irvine , Senior ASIC DV Engineer, Engineering , Irvine, California

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